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CML Semiconductor Products
PRODUCT INFORMATION
FX029
Dual Digitally Controlled Amplifier Array
Applications Cellular and PMR Communications Systems Automatic and Manual Test Equipment Remote Gain Adjustments Telephone Audio Settings Medical Equipment Audio and Data Gain Setting Applications
Publication D/029/4 November 2003 Provisional Issue
Features 2 Digitally Controlled Amplifiers Gain/Attenuation Range of 48dB + Output Mute, in 2dB Steps Gain/Attenuation Levels Set by Serial Interface Separate Fixed-Gain Uncommitted Amplifier 5 Volt Low-Power Operation
SERIAL CLOCK SERIAL DATA
LOAD/LATCH
STAGE 1 CONTROL REGISTER
Gain Control 1
SERIAL INTERFACE
STAGE 2 CONTROL REGISTER
Control 2
Gain
IN 1A IN 1B IN 1C
6
6
IN 2A
IN 2B
Stage 1
VBIAS
VBIAS
Stage 2 Stage 2 Inputs
FX029
Stage 1 Inputs
VDD VBIAS
VSS
Control 1
Control 2
+ VSS VSS
Stage 3
(UNCOMMITTED)
IN 3
Stage 3 Input
VBIAS
OUTPUTS
1A
1B
2
3
Fig.1 Functional Block Diagram
Brief Description
The FX029 single-chip Dual Digitally Controlled Amplifier Array can replace manual audio-level controls in most electronic applications including radio and line communications systems. The FX029 comprises two digitally controlled gain and attenuation stages, with each stage having 48 distinct gain steps (range; between -48dB and +48dB in 2dB steps) plus a MUTE state. Both gain stages have selectable inputs. This switching allows for selection of three different input signals to stage 1 and two to stage 2. Stage 1 also provides output switching. In addition to the two digitally controlled gain stages, there is a general purpose, uncommitted inverting amplifier; the gain of this particular amplifier is component controlled externally using negative feedback. Control of each gain stage section is accomplished through the serial interface. All switching is accomplished using controlled rise and fall times, thereby ensuring no annoying transients (clicks or pops). The FX029 requires a single 5 volt supply and is available in compact cerdip and small outline packages.
1
Pin Number
FX029 DW/J D5 1 1
Function
Serial Clock: This external clock input is used to "clock in" the control data. See Figure 4 for timing information. This input has an internal 1M pullup resistor.
2
4
Serial Data: Operation of the two amplifier stages (1 and 2) is controlled by the data entered serially at this pin. The data is entered (bit 13 to bit 0) on the rising edge of the external Serial Clock. The data format is described in Tables 1-3 and Figure 4. This input has an internal 1M pullup resistor.
3
5
Load/Latch: Governs the loading and execution of the serial control data. During serial data loading this input should be kept at a logical "1" to ensure that data rippling past the latches has no effect. When all 14 bits have been loaded this input should be strobed "1" to "0" to "1" to latch the new data in. Data is executed on the rising edge of this strobe.
4
6
IN 1A (Stage 1 Input 1): Analogue Input.
5
7
IN 1B (Stage 1 Input 2): Analogue Input.
6
8
IN 2A (Stage 2 Input 1): Analogue Input.
7
9
IN 2B (Stage 2 Input 2): Analogue Input.
8
12
VSS: Negative supply rail (GND).
9
13
VBIAS: The output of the on-chip bias circuitry, held at VDD/2.
10
16
IN 1C (Stage 1 Input 3): Analogue Input. Normally used for FSK data.
11
17
OUT 2 (Stage 2 Output): Analogue Output.
12
18
OUT 1B (Stage 1 Output 2): Analogue Output.
13
20
OUT 1A (Stage 1 Output 1): Analogue Output.
14
21
OUT 3 (Uncommitted Amplifier Output): Output from the general purpose uncommitted amplifier.
15
23
IN 3 (Uncommitted Amplifier Input): Inverting input to general purpose uncommitted amplifier.
16
24
VDD: Positive supply rail. A single +5-volt power supply is required.
2
Application Information
External Components
VDD
SERIAL CLOCK SERIAL DATA LOAD/LATCH IN 1A IN 1B IN 2A IN 2B C1 C2 C3 C4 VSS 8
1 2 3 4
16 15 14 13
VDD
IN 3 OUT 3
C7 VSS
OUT 1A OUT 1B OUT 2 C5 VBIAS IN 1C
FX029
5 6 7
DW/J
12 11 10 9
VSS
Fig.2 Recommended External Components
Component Recommendations Component Value C1 0.1F C2 0.1F C3 0.1F C4 0.1F C5 0.1F C6 Not Used C7 1.0F Tolerances 20% Input capacitors C1 to C5 are only required for ac input signals; dc input signals do not require these components. The gain of the uncommitted stage (3) is set by external components employed around the input and output pins (see Specification page). Application Recommendations To avoid noise and instability the following practices are recommended: (a) Use a clean, well-regulated power supply. (b) Keep tracks short. (c) Inputs and outputs should be shielded wherever possible. (d) Analogue tracks should not run parallel to digital tracks. (e) A "Ground Plane" connected to VSSwill assist in eliminating external pick-up on the channel input and output pins. (f) Avoid running high level outputs adjacent to low level inputs. (g) The serial clock should not be running consecutively when not in the process of actually loading data.
Serial Interface Timing
SERIAL CLOCK
t PWH t PWL
1ST CLOCK PULSE 14TH CLOCK PULSE
SERIAL DATA
t DS
D13
t DH
D12
D1
D0
LOAD/LATCH
t LLD
t LLO
Fig.3 Serial Timing Diagram - see Specification page for timing specifications
3
t LLW
Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/ Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed, 6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for output settings (D0-D3). This format is illustrated below in Figure 4. Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection and output settings, respectively.
D13
D12
D12
D10
D9
D8
D7
D6
D5 INPUT SELECT
D4
D3
D2
D1
D0
GAIN/ATTENUATION LEVEL CHANNEL ADDRESS
OUTPUT SETTINGS
Fig.4 Level-Controlling Data Word Format
D13 D12 D11 D10
Gain Set (dB) 0 0 0 0 0 0 MUTE 0 0 0 0 0 1 -48 0 0 0 0 1 0 -46 0 0 0 0 1 1 -44 0 0 0 1 0 0 -42 0 0 0 1 0 1 -40 0 0 0 1 1 0 -38 0 0 0 1 1 1 -36 0 0 1 0 0 0 -34 0 0 1 0 0 1 -32 0 0 1 0 1 0 -30 0 0 1 0 1 1 -28 0 0 1 1 0 0 -26 0 0 1 1 0 1 -24 0 0 1 1 1 0 -22 0 0 1 1 1 1 -20 0 1 0 0 0 0 -18 0 1 0 0 0 1 -16 0 1 0 0 1 0 -14 0 1 0 0 1 1 -12 0 1 0 1 0 0 -10 0 1 0 1 0 1 -8 0 1 0 1 1 0 -6 0 1 0 1 1 1 -4 0 1 1 0 0 0 -2 0 1 1 0 0 1 0 Table 1 - Amplification/Attenuation Level
D9
D8
D13 D12 D11 D10
D9
D8
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Gain Set (dB) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 48 48
D7 0 1
0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Table 2 Stage and Input Selection
Stage Selected 1 2
D6
D5
D4 0 1 0 1 0 1 0 1
Inputs Selected none 1 2 1 and 2 3 1 and 3 2 and 3 1, 2 and 3
Output D1 1B 0 0 high Z 0 0 1 enabled 0 1 0 VSS 1 1 1 VBIAS 1 Table 3 Stage Output Selection
D3 D2
D0 0 1 0 1
Outputs 1A & 2 high Z enabled VSS VBIAS
4
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref. VSS = 0V) -0.3 to (VDD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA Total device dissipation (DW/J) @ TAMB 25C (D5) @ TAMB 25C Derating (DW/J) (D5) Operating temperature range: FX029DW/D5/J Storage temperature range: FX029D5 FX029DW/J 800mW Max. 550mW Max. 10mW/C 9mW/C -40C to +85C -40C to +85C -55C to +125C
Operating Characteristics
All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V, TAMB = 25C. External components as Figure 2. Audio 0dB ref. = 775mVrms
Characteristics
See Note
Min.
4.5 3.5 0.5 3.3 46.0 46.0 50.0 10.0 250 250 150 50.0 200 150 -
Typ.
5.0 3.0 1.0 1.0 0.35 60.0 48.0 48.0 2.0 10.0 1.0 0.35 60 -
Max.
5.5 1.5 2.0 0.5 0.4 2.0 0.5 0 2.0
Unit
V mA V V M kHz k % dB dB dB dB/step dB k mV kHz k % dB ns ns ns ns ns ns ns MHz
Supply Voltage Current (All Stages Operating) Digital Inputs 4 Input Logic "1" Input Logic "0" Digital Input Impedances Gain Control Amplifier Stages (Stages 1 and 2) Bandwidth (-3dB) 1 Output Impedance Total Harmonic Distortion 2, 5 Interstage Isolation Gain Attenuation Gain/Attenuation Step Size Step Error Input Impedance Input Referred Offset Voltage (VIOS) Uncommitted Amplifier (Stage 3) Bandwidth (-3dB) 3 Output Impedance Total Harmonic Distortion 3 Open Loop DC Gain Timing (See Figure 3) Serial Clock "High" Pulse Width (tPWH) Serial Clock "Low" Pulse Width (tPWL) Data Set-up Time (tDS) Data Hold Time (tDH) Load/Latch Delay (t LLD) Load/Latch Over-Time (tLLO) Load/Latch Pulse Width (tLLW) Serial Data Clock Frequency Notes 1. 2. 3. 4. 5. Gain set to maximum (+48.0dB). Gain Set 0dB. Input Level 1.0kHz, -3.0dB (549mVrms). Gain externally set to 10.0dB. Serial Clock, Serial Data and Load/Latch inputs. With a 100k load on the relevant output.
5
Package Outlines
The FX029 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of the Data Book. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top.
Handling Precautions
The FX029 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage.
FX029D5
24-Pin Plastic S.S.O.P.
NOT TO SCALE
Max. Body Length Max. Body Width
8.33mm 5.38mm
FX029DW 16-pin plastic S.O.I.C.
(D4)
FX029J
16-pin cerdip DIL
(J2)
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
10.49mm 7.59mm
Max. Body Length Max. Body Width
19.48mm 7.39mm
Ordering Information
FX029D5 FX029DW FX029J 24-pin plastic S.S.O.P. 16-pin plastic S.O.I.C. 16-pin cerdip (D4) (J2)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.
6
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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